By Bolaji Ojo
STMicroelectronics N.V. has unveiled plans to enhance its technological processes by advancing next-generation chip manufacturing technology at its Tours facility in France. The company said it has committed over $60 million to launch a cutting-edge Panel-Level Packaging (PLP) pilot line, with operations slated to commence in the third quarter of 2026.
The initiative is part of ST’s broader strategy to reshape its manufacturing footprint, focusing on advanced integration and packaging methods that bolster efficiency, flexibility, and scale. The new PLP line will feature collaboration among multidisciplinary experts, including process engineers and data scientists, working to redefine chip packaging and test technology across a broad range of applications, spanning radio frequency (RF), analog, power, and digital products.
“This investment in Tours advances an innovative approach to chip packaging and test manufacturing, aiming to boost productivity and flexibility for deployment across our entire product portfolio,” said Fabio Gualandris, president of quality, manufacturing, and technology at ST, in a statement. “It marks a significant milestone in our roadmap for heterogeneous integration — an efficient new path for scalable chip integration.”